
	Sun System Handbook	Home \| Systems \| Components \| General Info \| Search \| Feedback

Cycle5-SS

370-2335

0MB FRU

70MHz, 85MHz, 90MHz, 100MHz, 110MHz

Note -

1. AMD supplies 8 bit audio to backplane.
2. Serial A/B uses SS10 style Y cable.
3. Use 72 pin IPX, IPC, Classic style memory in S1 and S2.
4. Use 30 pin SPARC station1, 1+ & 2 style memory in ML 1-8 MR1-8.
5. FREQ SELECT GAL at U33 selects 70MHz to 110MHz frequency.
6. Solaris 2.3/SunOS 5.3 or Solaris 1.1.1 Version B/SunOS 4.1.4 is required.

Supported Memory

Sun supported memory for the different frequency Cycle boards.

SIZE

SIMM
SUN P/N

SPEED

CYCLE 5
70-90 MHz

CYCLE 5
100-110 MHz

CYCLE 5
125 MHz

30 PIN

1MB

501-1408

100ns

X

1MB

501-1697

80ns

X

4MB

501-1625

100ns

X

4MB

501-1739

80ns

X

X

72 PIN

4MB

501-1812

80ns

X

X

4MB

501-1991

60ns

X

X

X

16MB

501-1822

80ns

X

X

16MB

501-1915

80ns

X

X

16MB

501-2059

60ns

X

X

X

Physical Layout of memory as reported by POST.

BANK #	REPORTED CAPACITY	MEMORY LOCATION	INDIVIDUAL SIMM CAPACITY	P/N	MAX MEM	PHYSICAL SLOT LOCATION
BANK 0	8MB	8 SETS OF 1MB, 30 PIN SIMMS ML1 TO ML4 & MR1 TO MR4	1MB	501-1697 501-1408	8MB	8 PHYSICAL 30 PIN SLOTS LABELED ML1 TO ML4 AND MR1 TO MR4
BANK 0	32MB	8 SETS OF 4MB, 30 PIN SIMMS ML1 TO ML4 & MR1 TO MR4	4MB	501-1625 501-1739	32MB	8 PHYSICAL 30 PIN SLOTS LABELED ML1 TO ML4 AND MR1 TO MR4
BANK 1	8MB	8 SETS OF 1MB, 30 PIN SIMMS ML5 TO ML8 & MR5 TO MR8	1MB	501-1697 501-1408	8MB	8 PHYSICAL 30 PIN SLOTS LABELED ML5 TO ML8 AND MR5 TO MR8
BANK 1	32MB	8 SETS OF 4MB, 30 PIN SIMMS ML5 TO ML8 & MR5 TO MR8	4MB	501-1625 501-1739	32MB	8 PHYSICAL 30 PIN SLOTS LABELED ML5 TO ML8 AND MR5 TO MR8
BANK 2	8MB	2 SETS OF 4MB, 72 PIN SIMMS S0 TO S1	4MB	501-1812 501-1991	8MB	2 PHYSICAL 72 PIN SLOTS LABELED S0 AND S1
BANK 2	32MB	2 SETS OF 16MB, 72 PIN SIMMS S0 TO S1	16MB	501-1915 501-1822 501-2059	32MB	2 PHYSICAL 72 PIN SLOTS LABELED S0 AND S1

Note - To obtain reported memory capacity the NVRAM parameter diag-switch? is set to true, forcing a diagnostic power on.

DIP Settings

The FREQ SELECT GAL located at U33 sets the maximum microSPARC II frequency with up to three additional lower frequencies selectable via DIP SW1, PINS 3 AND 4.

DIP	PINS	SETTING	DESCRIPTION 70MHz FREQ GAL	DESCRIPTION 85MHz FREQ GAL	DESCRIPTION 90MHz FREQ GAL
SW1	3	OFF*	70 MHz SBus23.3MHz	85 MHz SBus21.25MHz	90 MHz SBus22.5MHz
	4	OFF*
	3	ON	70 MHz SBus23.3MHz	70MHz SBus23.3MHz	90MHz SBus22.5MHz
	4	OFF
	3	OFF	70 MHz SBus23.3MHz	70MHz SBus23.3MHz	85MHz SBus21.25MHz
	4	ON
	3	ON	70 MHz SBus23.3MHz	70MHz SBus23.3MHz	70MHz SBus23.3MHz
	4	ON

DIP	PINS	SETTING	DESCRIPTION 100MHz FREQ GAL	DESCRIPTION 110MHz FREQ GAL
SW1	3	OFF*	100MHz SBus22.5MHz	110MHz SBus22MHz
	4	OFF*
	3	OFF	90MHz SBus22.5MHz	100MHz SBus22.5MHz
	4	ON
	3	ON	85MHz SBus21.25MHz	90MHz SBus22.5MHz
	4	OFF
	3	ON	70MHz SBus23.3MHz	85MHz SBus21.25MHz
	4	ON

* Default Setting for the Cycle5-SS

Jumper/DIP Settings-Continued

The DIP SW1, PINS 1 and 2 control the microSPARC II controller wait states, with the following settings.

JUMPER/DIP	PINS	SETTING	DESCRIPTION
SW1	1	OFF*	spd_sel<0>=0 spd_sel<1>=0
	2	OFF*	spd_sel<0>=0 spd_sel<1>=0
	1	ON	spd_sel<0>=0 spd_sel<1>=1
	2	OFF	spd_sel<0>=0 spd_sel<1>=1
	1	OFF	spd_sel<0>=1 spd_sel<1>=0
	2	ON	spd_sel<0>=1 spd_sel<1>=0
	1	ON	spd_sel<0>=1 spd_sel<1>=1
	2	ON	spd_sel<0>=1 spd_sel<1>=1
GND1	N/A	N/A	GROUND TEST POINT
GND2	N/A	N/A	GROUND TEST POINT
GND3	N/A	N/A	GROUND TEST POINT
GND4	N/A	N/A	GROUND TEST POINT

* Default setting for the Cycle5-SS.


Copyright 1994-2000 Sun Microsystems, Inc., 901 San Antonio Road, Palo Alto, CA 94303 USA. All rights reserved. Legal Terms Privacy Policy Feedback